Technology

Can SAP Labs’ AI plan accelerate cloud migration?

Nestled in the sun-kissed hills of Provence, just north of Cannes and Antibes, is Sophia Antipolis, a renowned technology and science hub that is home to SAP subsidiary SAP Labs France. There are worse places to work. Surrounded by Aleppo pines and the odd palm, this modern building has been chosen to host the company’s…

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Lords say government must ‘go beyond’ current approach to LLMs

A Lords committee is calling on the government to make market competition in artificial intelligence (AI) “an explicit policy objective” while criticising its “inadequate and deteriorating” position on the use of copyrighted material in large language models (LLMs).Following the release of a government response to the Communications and Digital Committee’s report on LLMs and generative…

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Samsung Starts Mass Production of 9th Generation V-NAND: 1Tb 3D TLC NAND

Samsung Electronics has started mass production of its 9th generation of V-NAND memory. The first dies based on their latest NAND tech come in a 1 Tb capacity using a triple-level cell (TLC) architecture, with data transfer rates as high as 3.2 GT/s. The new 3D TLC NAND memory will initially be used to build…

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Apple’s new CTF rules protect more small developers from the iPhone sideloading tax

Apple announced a new Core Technology Fee (CTF) a few months ago when it confirmed iPhone sideloading was coming to the European Union (EU). The fee amounts to €0.50 per app download after the first one million annual downloads. It applies to developers who want to sell apps outside the App Store in competing marketplaces…

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Report: Seagate, Western Digital Hike HDD Prices Amid Surge In Demand

Seagate Technology has reportedly notified its customers abouts its plans to raise prices on new hard drive orders and for demands that exceed prior agreements, echoing a similar move by Western Digital, which increased its prices earlier this month. These changes come in response to a surge in demand for high-capacity HDDs and constraints in…

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TSMC 2nm Update: N2 In 2025, N2P Loses Backside Power, and NanoFlex Brings Optimal Cells

Taiwan Semiconductor Manufacturing Co. provided several important updates about its upcoming process technologies at its North American Technology Symposium 2024. At a high level, TSMC’s 2 nm plans remain largely unchanged: the company is on track to start volume production of chips on it’s first-generation GAAFET N2 node in the second half of 2025, and N2P…

TSMC 2nm Update: N2 In 2025, N2P Loses Backside Power, and NanoFlex Brings Optimal Cells Read More »

TSMC Preps Cheaper 4nm N4C Process For 2025, Aiming For 8.5% Cost Reduction

While the bulk of attention on TSMC is aimed at its leading-edge nodes, such as N3E and N2, loads of chips will continue to be made using more mature and proven process technologies for years to come. Which is why TSMC has continued to refine its existing nodes, including its current-generation 5nm-class offerings. To that…

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TSMC’s System-on-Wafer Platform Goes 3D: CoW-SoW Stacks Up the Chips

TSMC has been offering its System-on-Wafer integration technology, InFO-SoW, since 2020. For now, only Cerebras and Tesla have developed wafer scale processor designs using it, as while they have fantastic performance and power efficiency, wafer-scale processors are extremely complex to develop and produce. But TSMC believes that not only will wafer-scale designs ramp up in…

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TSMC Jumps Into Silicon Photonics, Lays Out Roadmap For 12.8 Tbps COUPE On-Package Interconnect

Optical connectivity – and especially silicon photonics – is expected to become a crucial technology to enable connectivity for next-generation datacenters, particularly those designed HPC applications. With ever-increasing bandwidth requirements needed to keep up with (and keep scaling out) system performance, copper signaling alone won’t be enough to keep up. To that end, several companies are developing…

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TSMC Readies 8x Reticle Super Carrier Interposer For Next-Gen Chips Twice as Large As Today’s

TSMC is no stranger to building big chips. Besides the ~800mm2 reticle limit of their normal logic processes, the company already produces even larger chips by fitting multiple dies on to a single silicon interposer, using their chip-on-wafer-on-substrate (CoWoS) technology. But even with current-gen CoWoS allowing for interposers up to 3.3x TSMC’s reticle limit, TSMC…

TSMC Readies 8x Reticle Super Carrier Interposer For Next-Gen Chips Twice as Large As Today’s Read More »

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