TSMC 2023 Technology Symposium

Pumped Up Procs: TSMC Planning Chips 3x Bigger Than Today

TSMC is developing a new version of its Chip-On-Wafer-On-Substrate-L (CoWoS-L) that will enable it to build extremely large interposers — which it calls Super Carrier Interposers — that pushing the boundaries of current system-in-package (SiPs) sizes to levels never seen before. The next-generation CoWoS technology, planned to be qualified in 2025, will potentially increase the…

TSMC

TSMC Readies N2P and N2X: 2nm with Enhanced Performance

At the 2023 North American Technology Symposium TSMC revealed more information about its upcoming 2nm-class process technologies set to be production ready in 2025 – 2026. The world’s largest foundry plans to expand its N2 family with N2P that will get a backside power rail and promises to boost performance, reduce power consumption, and increase transistor density. In addition, TSMC…

ASML

TSMC Might Cut 3nm Prices to Lure AMD, Nvidia

Although TSMC’s N3 (3nm-class) family of fabrication processes brings a number of benefits in terms of performance and power, the very high costs of the foundry’s initial N3 node hampers widespread adoption. Unsurprisingly, the company is rumored to be preparing to lower its quotes for 3nm production to stimulate interest from chip designers, according to a report…